Simple Dual-Port RAM
Infer a small synchronous-write, asynchronous-read dual-port memory.
Task
Write wdata to waddr on a rising clock edge when we is high. Independently expose the location selected by raddr on rdata.
Examples
- write address 3 with 0xA5 -> reading address 3 returns 0xA5
Constraints
- One write port and one read port.
- Parameterized width and depth.
- Synthesizable RTL only.
What this problem is testing
A strong answer translates the requirement into synthesizable state and combinational logic, states reset and update semantics precisely, and handles boundary conditions rather than only the nominal case.
Interview habit: before coding, state reset behavior, the state that must be stored, and the conditions that update each output.
Verification plan
- Check reset or initialization before normal operation.
- Exercise the nominal sequence cycle by cycle.
- Test boundaries such as zero, maximum count, wraparound, full/empty, or simultaneous controls when they apply.
- Prove the design holds state when an enable or qualifying condition is absent.
Edge cases worth testing
- Read-after-write behavior.
- Address boundary values.
- Simultaneous accesses or collisions when the interface permits them.
Common mistakes
- Incomplete combinational assignments that infer a latch.
- Blocking/non-blocking assignments that do not match combinational versus sequential intent.
- Parameter-width and boundary errors.
- Passing the happy path while missing reset, overflow, simultaneous operations, or illegal requests.
Interview follow-up questions
- How would you parameterize this design without introducing width or boundary bugs?
- What changes if reset timing or polarity changes?
- What read-during-write behavior do you expect from the target memory?
Concepts to review
memory, ram, bram, dual-port
Open Simple Dual-Port RAM in the HDLForge interactive editor.
Related problems
- 2:1 Multiplexer — Easy
- Parameterized Counter — Easy
- Priority Encoder — Medium
- Synchronous FIFO — Hard
- Shift Register — Easy
Explore the RTL Design Practice & Interview Preparation hub.