FPGA · Advanced

FPGA Packet Parser and Statistics Engine

Build a streaming Ethernet-style header parser that extracts fields, classifies packets and maintains counters at one word per cycle.

Key skills

Implementation plan

• Design for a target clock and realistic FPGA resources rather than simulation alone.
• Plan clock/reset domains, external interfaces and timing constraints early.
• Verify functionality before implementation, then inspect utilization and timing reports.
• Measure throughput/latency and document hardware-specific issues such as CDC or BRAM inference.

Verification plan

• Create a self-checking reference for the expected behavior before optimizing the RTL.
• Test reset and initialization, nominal operation, boundary conditions and back-to-back activity.
• Inject stalls, invalid requests or other stress cases when the interface permits them.
• Keep regression results, waveforms and failure notes so the project demonstrates debugging as well as coding.

Suggested deliverables

• RTL
• simulation
• throughput report
• FPGA utilization/timing results

Problems to practise first

What to discuss in an interview

• The architecture you chose and the alternatives you rejected.
• The hardest bug or corner case and how you found it.
• How you verified correctness beyond one successful waveform.
• Timing, area, latency, coverage or protocol trade-offs relevant to the project.