RTL design / memory

Verilog FIFO Design Guide

A FIFO is a compact interview problem that exposes whether you can reason about state, memory, boundary conditions and simultaneous controls. The cleanest design starts from explicit enqueue/dequeue events and derives pointer and occupancy updates from those events.

Core design rules

• Define write_fire = wr_en && !full and read_fire = rd_en && !empty before updating any state.
• Do not advance pointers for rejected reads or writes.
• Handle simultaneous successful read/write without accidentally changing occupancy.
• Make full and empty semantics explicit for the chosen pointer/count implementation.

Implementation path

• Use a small synchronous FIFO first: memory array, read pointer, write pointer and occupancy count.
• Parameterize width and depth only after the fixed-size behavior is correct.
• Decide whether read data is registered or combinational and keep the testbench aligned with that choice.
• For FPGA-oriented versions, consider how the memory style maps to BRAM and whether non-power-of-two depth is required.

Verification checklist

• Reset to empty and verify the flags before the first transaction.
• Fill to capacity, attempt an extra write and prove state does not corrupt.
• Drain to empty, attempt an extra read and prove the read pointer does not move.
• Run simultaneous read/write at empty, full and mid-occupancy boundaries.

Useful RTL / verification pattern

wire write_fire = wr_en && !full;
wire read_fire  = rd_en && !empty;

case ({write_fire, read_fire})
  2'b10: count <= count + 1'b1;
  2'b01: count <= count - 1'b1;
  default: count <= count;
endcase

Practice with executable problems

Turn it into a project