Clock Domain Crossing (CDC) Interview Guide
Review metastability, synchronizer chains, pulse transfer, multi-bit CDC, handshakes and asynchronous FIFOs for digital design and FPGA interviews.
Metastability
A receiving flip-flop can violate setup or hold time when sampling an asynchronous transition. A two-flop synchronizer reduces the probability that metastability propagates into destination logic.
Single-bit versus multi-bit CDC
Single-bit controls can often use synchronizer chains. Multi-bit data generally needs a protocol such as a handshake, Gray-coded pointer scheme or asynchronous FIFO rather than synchronizing every bit independently.
Questions to practise
Why are two flip-flops commonly used? When is a pulse synchronizer needed? Why is synchronizing each bit of a bus unsafe? How do asynchronous FIFO pointers cross domains?
Practise on HDLForge
Browse related hardware design problems and follow the structured roadmap.