SystemVerilog Assertions (SVA) Practice
Practice SystemVerilog Assertions with clocked properties, implication, bounded response, reset handling, one-hot checks and stability requirements.
What interviewers usually look for
SVA questions test temporal reasoning: exactly when signals are sampled, overlapped versus non-overlapped implication, reset disabling, and whether an assertion can pass vacuously.
How to practise this topic
- Write one passing trace and one deliberately failing trace.
- Check the exact cycle where the antecedent becomes true and where the consequent starts.
- Exercise reset while the property is active.
Practice problems
Valid Must Eventually Handshake
Write an assertion for a ready/valid interface.Reset Clears State
Verify that a synchronous reset clears a counter on the next clock edge.Payload Stable While Stalled
Assert that a source cannot change its payload while valid is high and ready is low.One-Hot Grant Assertion
Assert that an arbiter never grants more than one requester.No FIFO Overflow Assertion
Assert that a write is never attempted while the FIFO is full.No FIFO Underflow Assertion
Assert that a read is never attempted while the FIFO is empty.Bounded Request Response
Require a response within a bounded number of cycles.Mutual Exclusion Assertion
Assert that read_active and write_active are never high together.One-Cycle Pulse Width
Assert that done is never high for two consecutive cycles.AXI-Lite Protocol Assertions
Add protocol properties that catch payload instability and missing responses.RISC-V Core Assertions
Check key architectural invariants around x0 and retirement stability.AXI Crossbar Protocol Assertions
Check grant exclusivity and stalled payload stability in the crossbar.
Write an assertion for a ready/valid interface.Reset Clears State
Verify that a synchronous reset clears a counter on the next clock edge.Payload Stable While Stalled
Assert that a source cannot change its payload while valid is high and ready is low.One-Hot Grant Assertion
Assert that an arbiter never grants more than one requester.No FIFO Overflow Assertion
Assert that a write is never attempted while the FIFO is full.No FIFO Underflow Assertion
Assert that a read is never attempted while the FIFO is empty.Bounded Request Response
Require a response within a bounded number of cycles.Mutual Exclusion Assertion
Assert that read_active and write_active are never high together.One-Cycle Pulse Width
Assert that done is never high for two consecutive cycles.AXI-Lite Protocol Assertions
Add protocol properties that catch payload instability and missing responses.RISC-V Core Assertions
Check key architectural invariants around x0 and retirement stability.AXI Crossbar Protocol Assertions
Check grant exclusivity and stalled payload stability in the crossbar.
How to use this topic
Start with easier problems, implement or reason through the task without looking at a solution, then revisit medium and hard problems. Use the HDLForge roadmap to combine this topic with adjacent skills.
Follow the HDLForge roadmap or browse the complete problem set.
Related implementation guides
- SVA Handshake Assertions Guide — Write SystemVerilog Assertions for ready/valid and bus handshakes: VALID hold, payload stability, responses, reset disabling and backpressure.
- AXI-Lite Verification Guide — Learn how to verify AXI-Lite RTL with independent channel handshakes, assertions, scoreboards, backpressure tests and executable HDLForge practice.