RISC-V Core Assertions
Check key architectural invariants around x0 and retirement stability.
Task
Assert that x0 is always zero and that retirement payload stays stable while retire_valid is high and retire_ready is low.
Examples
- Complete the required behavior and preserve it under the stated control conditions.
Constraints
- Use synthesizable SystemVerilog unless this is a verification-only stage.
What this problem is testing
SVA questions test temporal reasoning: exactly when signals are sampled, overlapped versus non-overlapped implication, reset disabling, and whether an assertion can pass vacuously.
Interview habit: before coding, state reset behavior, the state that must be stored, and the conditions that update each output.
Verification plan
- Write one passing trace and one deliberately failing trace.
- Check the exact cycle where the antecedent becomes true and where the consequent starts.
- Exercise reset while the property is active.
- Use cover or directed stimulus when useful to prove the antecedent can actually occur.
Common mistakes
- Choosing |-> versus |=> by habit.
- Forgetting disable iff or mishandling reset.
- Allowing vacuous success because the antecedent never occurs.
- Using unbounded eventuality when the protocol has a finite response requirement.
Interview follow-up questions
- Would overlapped or non-overlapped implication be correct here, and why?
- How would you detect or avoid vacuous success?
Concepts to review
RISC-V, SVA, processor verification
Open RISC-V Core Assertions in the HDLForge interactive editor.
Related problems
- Valid Must Eventually Handshake — Medium
- Reset Clears State — Easy
- Payload Stable While Stalled — Medium
- One-Hot Grant Assertion — Easy
- No FIFO Overflow Assertion — Easy
Explore the SystemVerilog Assertions (SVA) Practice hub.