Reset Clears State
Verify that a synchronous reset clears a counter on the next clock edge.
Task
Write an assertion connecting reset with the expected zero state.
Examples
- reset=1 at edge → count=0 after edge
Constraints
- Account for synchronous reset semantics.
What this problem is testing
SVA questions test temporal reasoning: exactly when signals are sampled, overlapped versus non-overlapped implication, reset disabling, and whether an assertion can pass vacuously.
Interview habit: before coding, state reset behavior, the state that must be stored, and the conditions that update each output.
Verification plan
- Write one passing trace and one deliberately failing trace.
- Check the exact cycle where the antecedent becomes true and where the consequent starts.
- Exercise reset while the property is active.
- Use cover or directed stimulus when useful to prove the antecedent can actually occur.
Edge cases worth testing
- A trace where the antecedent occurs but the consequent fails.
- A trace where the antecedent never occurs, to inspect vacuity.
- Reset asserted during active operation.
- The first cycle after reset is released.
Common mistakes
- Choosing |-> versus |=> by habit.
- Forgetting disable iff or mishandling reset.
- Allowing vacuous success because the antecedent never occurs.
- Using unbounded eventuality when the protocol has a finite response requirement.
Interview follow-up questions
- Would overlapped or non-overlapped implication be correct here, and why?
- How would you detect or avoid vacuous success?
Concepts to review
assertion, reset
Open Reset Clears State in the HDLForge interactive editor.
Related problems
- Valid Must Eventually Handshake — Medium
- Asynchronous-Assert Reset Synchronizer — Medium
- Clock and Reset Generator — Easy
- Payload Stable While Stalled — Medium
- One-Hot Grant Assertion — Easy
Explore the SystemVerilog Assertions (SVA) Practice hub.