RISC-V Functional Coverage
Measure instruction-class and destination-register diversity during regression.
Task
Create coverpoints for opcode class, destination register and register-write enable, and cross opcode with register-write behavior.
Examples
- Complete the required behavior and preserve it under the stated control conditions.
Constraints
- Use synthesizable SystemVerilog unless this is a verification-only stage.
Concepts to review
RISC-V, coverage, cross coverage
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Related problems
- Basic Coverpoint Bins — Easy
- Cross Operation and Size — Medium
- Illegal Coverage Bin — Medium
- Ignore Uninteresting Coverage Range — Easy
- State Transition Coverage — Medium