No FIFO Underflow Assertion
Assert that a read is never attempted while the FIFO is empty.
Task
Whenever empty is high, rd_en must be low.
Examples
- Implement the requested verification structure or behavior.
Constraints
- Use SystemVerilog.
- Keep the code focused on the requested verification concept.
What this problem is testing
SVA questions test temporal reasoning: exactly when signals are sampled, overlapped versus non-overlapped implication, reset disabling, and whether an assertion can pass vacuously.
Interview habit: before coding, state reset behavior, the state that must be stored, and the conditions that update each output.
Verification plan
- Write one passing trace and one deliberately failing trace.
- Check the exact cycle where the antecedent becomes true and where the consequent starts.
- Exercise reset while the property is active.
- Use cover or directed stimulus when useful to prove the antecedent can actually occur.
Edge cases worth testing
- Write when full and read when empty.
- Simultaneous read and write.
- Pointer wraparound and transitions into and out of full/empty.
Common mistakes
- Choosing |-> versus |=> by habit.
- Forgetting disable iff or mishandling reset.
- Allowing vacuous success because the antecedent never occurs.
- Using unbounded eventuality when the protocol has a finite response requirement.
Interview follow-up questions
- Would overlapped or non-overlapped implication be correct here, and why?
- How would you detect or avoid vacuous success?
- How would this change for an asynchronous FIFO?
Concepts to review
sva, fifo, underflow
Open No FIFO Underflow Assertion in the HDLForge interactive editor.
Related problems
- Synchronous FIFO — Hard
- Valid Must Eventually Handshake — Medium
- Reset Clears State — Easy
- Counted Synchronous FIFO — Hard
- FIFO Almost-Full / Almost-Empty Flags — Medium
Explore the SystemVerilog Assertions (SVA) Practice hub.