Three-Stage Pipelined RISC-V Core
Implement an RV32I processor with fetch/decode/execute-style staging, hazard handling, forwarding or stalls, branches and a simple memory interface.
Why build it: Strong evidence of RTL design, control-path reasoning and processor fundamentals.
Key skills
Implementation plan
- Turn the requirements into a block diagram and explicit state/data-path decisions.
- Define interfaces, reset behavior, widths and latency before coding.
- Build self-checking simulation for nominal and boundary cases.
- Review synthesis/timing consequences and document the trade-offs you made.
Verification plan
- Create a self-checking reference for the expected behavior before optimizing the RTL.
- Test reset and initialization, nominal operation, boundary conditions and back-to-back activity.
- Inject stalls, invalid requests or other stress cases when the interface permits them.
- Keep regression results, waveforms and failure notes so the project demonstrates debugging as well as coding.
Suggested deliverables
- RTL
- testbench
- block diagram
- timing/area summary
- ISA regression results
Problems to practise first
What to discuss in an interview
- The architecture you chose and the alternatives you rejected.
- The hardest bug or corner case and how you found it.
- How you verified correctness beyond one successful waveform.
- Timing, area, latency, coverage or protocol trade-offs relevant to the project.