RISC-V Core Verification
Verify an RV32I core using directed and constrained-random instruction streams, architectural scoreboarding, assertions and coverage across instruction classes and hazards.
Why build it: Demonstrates processor verification, debug discipline and coverage-driven thinking.
Key skills
Implementation plan
- Write a concise verification plan before building the environment.
- Separate stimulus, observation, prediction and checking responsibilities.
- Add assertions for protocol invariants and functional coverage for meaningful scenarios.
- Run regression seeds, classify failures and document coverage closure.
Verification plan
- Create a self-checking reference for the expected behavior before optimizing the RTL.
- Test reset and initialization, nominal operation, boundary conditions and back-to-back activity.
- Inject stalls, invalid requests or other stress cases when the interface permits them.
- Keep regression results, waveforms and failure notes so the project demonstrates debugging as well as coding.
Suggested deliverables
- test plan
- reference model/checker
- random tests
- coverage closure report
Problems to practise first
What to discuss in an interview
- The architecture you chose and the alternatives you rejected.
- The hardest bug or corner case and how you found it.
- How you verified correctness beyond one successful waveform.
- Timing, area, latency, coverage or protocol trade-offs relevant to the project.