AXI4 Interconnect / Crossbar
Build a two-master, three-slave AXI-Lite interconnect with address decoding, arbitration, ownership locking, response routing and DECERR handling.
Why build it: Demonstrates the control and protocol logic behind scalable SoC fabrics.
Key skills
Implementation plan
- Start with a memory map, interfaces and ownership of each transaction path.
- Implement and verify blocks independently before subsystem integration.
- Exercise software-visible reset/status/error behavior and bus backpressure.
- Finish with an end-to-end firmware or transaction-level demonstration.
Verification plan
- Create a self-checking reference for the expected behavior before optimizing the RTL.
- Test reset and initialization, nominal operation, boundary conditions and back-to-back activity.
- Inject stalls, invalid requests or other stress cases when the interface permits them.
- Keep regression results, waveforms and failure notes so the project demonstrates debugging as well as coding.
Suggested deliverables
- RTL
- address map
- contention tests
- latency notes
What to discuss in an interview
- The architecture you chose and the alternatives you rejected.
- The hardest bug or corner case and how you found it.
- How you verified correctness beyond one successful waveform.
- Timing, area, latency, coverage or protocol trade-offs relevant to the project.