RTL Design · Medium · Verilog, SystemVerilog, VHDL

Elastic Pipeline Register

Implement a single-stage pipeline register with an aligned valid bit.

Task

Capture in_data whenever in_valid is asserted and produce the captured value with out_valid on the next cycle.

Examples

• in_valid with 8'h5A -> out_valid next cycle with 8'h5A
• in_valid=0 -> out_valid deasserts next cycle

Constraints

• Synchronous active-high reset.
• Accept a new input every cycle.
• Data width is parameterized.

What this problem is testing

A strong answer translates the requirement into synthesizable state and combinational logic, states reset and update semantics precisely, and handles boundary conditions rather than only the nominal case.

Verification plan

• Check reset or initialization before normal operation.
• Exercise the nominal sequence cycle by cycle.
• Test boundaries such as zero, maximum count, wraparound, full/empty, or simultaneous controls when they apply.
• Prove the design holds state when an enable or qualifying condition is absent.

Edge cases worth testing

• An immediately preceding dependency.
• A dependency that can be forwarded versus one that requires a stall.

Common mistakes

• Incomplete combinational assignments that infer a latch.
• Blocking/non-blocking assignments that do not match combinational versus sequential intent.
• Parameter-width and boundary errors.
• Passing the happy path while missing reset, overflow, simultaneous operations, or illegal requests.

Interview follow-up questions

• How would you parameterize this design without introducing width or boundary bugs?
• What changes if reset timing or polarity changes?

Concepts to review

pipeline, valid, throughput

Open Elastic Pipeline Register in the HDLForge interactive editor.

Related problems

• 2:1 Multiplexer — Easy
• Parameterized Counter — Easy
• Priority Encoder — Medium
• Synchronous FIFO — Hard
• Shift Register — Easy

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