Async FIFO Dual-Port Memory
Create storage that can be written and read from different clock domains.
Task
Build a small dual-port memory with a write port clocked by `wclk` and an independent read port clocked by `rclk`.
Examples
- w_en=1 at wclk edge → memory location updates
- r_en=1 at rclk edge → rdata captures selected location
Constraints
- Use separate always_ff blocks for the two clocks.
- Do not synchronize the payload bus through flip-flops.
- Parameterize width and address width.
What this problem is testing
A strong answer translates the requirement into synthesizable state and combinational logic, states reset and update semantics precisely, and handles boundary conditions rather than only the nominal case.
Interview habit: before coding, state reset behavior, the state that must be stored, and the conditions that update each output.
Verification plan
- Check reset or initialization before normal operation.
- Exercise the nominal sequence cycle by cycle.
- Test boundaries such as zero, maximum count, wraparound, full/empty, or simultaneous controls when they apply.
- Prove the design holds state when an enable or qualifying condition is absent.
Edge cases worth testing
- Write when full and read when empty.
- Simultaneous read and write.
- Pointer wraparound and transitions into and out of full/empty.
- A transition close to the destination clock edge.
- A pulse shorter than a destination clock period.
- Read-after-write behavior.
Common mistakes
- Incomplete combinational assignments that infer a latch.
- Blocking/non-blocking assignments that do not match combinational versus sequential intent.
- Parameter-width and boundary errors.
- Passing the happy path while missing reset, overflow, simultaneous operations, or illegal requests.
Interview follow-up questions
- How would you parameterize this design without introducing width or boundary bugs?
- What changes if reset timing or polarity changes?
- What read-during-write behavior do you expect from the target memory?
Concepts to review
FIFO, CDC, memory
Open Async FIFO Dual-Port Memory in the HDLForge interactive editor.
Related problems
- 2:1 Multiplexer — Easy
- Parameterized Counter — Easy
- Priority Encoder — Medium
- Synchronous FIFO — Hard
- Shift Register — Easy
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