RTL Design · Medium · SystemVerilog

AXI-Lite W Channel Capture

Accept write data independently from the write address.

Task

Capture `WDATA` and `WSTRB` when `WVALID && WREADY` handshakes. Keep a `data_pending` flag until the write is committed.

Examples

• WVALID=1 and WREADY=1 → save WDATA/WSTRB
• AW can arrive before or after this handshake

Constraints

• Do not require AWVALID at the same time.
• Only assert WREADY when no data is pending.
• Reset clears data_pending.

What this problem is testing

A strong answer translates the requirement into synthesizable state and combinational logic, states reset and update semantics precisely, and handles boundary conditions rather than only the nominal case.

Verification plan

• Check reset or initialization before normal operation.
• Exercise the nominal sequence cycle by cycle.
• Test boundaries such as zero, maximum count, wraparound, full/empty, or simultaneous controls when they apply.
• Prove the design holds state when an enable or qualifying condition is absent.

Edge cases worth testing

• VALID held while READY is low.
• READY asserted before VALID.
• Back-to-back transfers without an idle cycle.

Common mistakes

• Incomplete combinational assignments that infer a latch.
• Blocking/non-blocking assignments that do not match combinational versus sequential intent.
• Parameter-width and boundary errors.
• Passing the happy path while missing reset, overflow, simultaneous operations, or illegal requests.

Interview follow-up questions

• How would you parameterize this design without introducing width or boundary bugs?
• What changes if reset timing or polarity changes?

Concepts to review

AXI4-Lite, write-data, handshake

Open AXI-Lite W Channel Capture in the HDLForge interactive editor.

Related problems

• 2:1 Multiplexer — Easy
• Parameterized Counter — Easy
• Priority Encoder — Medium
• Synchronous FIFO — Hard
• Shift Register — Easy

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