Pipeline Hazard Control Integration
Combine stall and redirect decisions into coherent controls for the PC and stage registers.
Task
Generate PC enable, IF/ID enable, IF/ID flush and ID/EX bubble controls. A taken branch flushes younger work; a load-use hazard freezes fetch/decode and bubbles execute.
Examples
- load_stall=1 → pc_enable=0, ifid_enable=0, idex_bubble=1.
- branch_taken=1 → ifid_flush=1 and idex_bubble=1.
Constraints
- Branch redirect must not leave younger instructions alive.
- Stall freezes PC and IF/ID.
- Keep the logic purely combinational.
What this problem is testing
A strong answer translates the requirement into synthesizable state and combinational logic, states reset and update semantics precisely, and handles boundary conditions rather than only the nominal case.
Interview habit: before coding, state reset behavior, the state that must be stored, and the conditions that update each output.
Verification plan
- Check reset or initialization before normal operation.
- Exercise the nominal sequence cycle by cycle.
- Test boundaries such as zero, maximum count, wraparound, full/empty, or simultaneous controls when they apply.
- Prove the design holds state when an enable or qualifying condition is absent.
Common mistakes
- Incomplete combinational assignments that infer a latch.
- Blocking/non-blocking assignments that do not match combinational versus sequential intent.
- Parameter-width and boundary errors.
- Passing the happy path while missing reset, overflow, simultaneous operations, or illegal requests.
Interview follow-up questions
- How would you parameterize this design without introducing width or boundary bugs?
- What changes if reset timing or polarity changes?
Concepts to review
RISC-V, pipeline control, integration
Open Pipeline Hazard Control Integration in the HDLForge interactive editor.
Related problems
- 2:1 Multiplexer — Easy
- Parameterized Counter — Easy
- Priority Encoder — Medium
- Synchronous FIFO — Hard
- Shift Register — Easy
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