RTL Design · Medium · SystemVerilog

AXI Crossbar Address Decoder

Decode a 32-bit request address to one of three AXI-Lite slaves.

Task

Map 0x0000_0000-0x0000_FFFF to slave 0, 0x1000_0000-0x1000_FFFF to slave 1, 0x2000_0000-0x2000_FFFF to slave 2, otherwise assert decode_error.

Examples

Constraints

What this problem is testing

A strong answer translates the requirement into synthesizable state and combinational logic, states reset and update semantics precisely, and handles boundary conditions rather than only the nominal case.

Interview habit: before coding, state reset behavior, the state that must be stored, and the conditions that update each output.

Verification plan

Common mistakes

Interview follow-up questions

Concepts to review

AXI, crossbar, address decode

Open AXI Crossbar Address Decoder in the HDLForge interactive editor.

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