RTL Design · Easy · SystemVerilog

2-bit Saturating Counter

Implement the classic four-state branch-direction predictor.

Task

Increment toward strongly taken on taken outcomes and decrement toward strongly not-taken on not-taken outcomes. Never wrap.

Examples

• Complete the required behavior and preserve it under the stated control conditions.

Constraints

• Use synthesizable SystemVerilog unless this is a verification-only stage.

What this problem is testing

A strong answer translates the requirement into synthesizable state and combinational logic, states reset and update semantics precisely, and handles boundary conditions rather than only the nominal case.

Verification plan

• Check reset or initialization before normal operation.
• Exercise the nominal sequence cycle by cycle.
• Test boundaries such as zero, maximum count, wraparound, full/empty, or simultaneous controls when they apply.
• Prove the design holds state when an enable or qualifying condition is absent.

Edge cases worth testing

• Maximum value and wraparound.
• Enable low while the counter would otherwise advance.
• Reset coincident with another control.

Common mistakes

• Incomplete combinational assignments that infer a latch.
• Blocking/non-blocking assignments that do not match combinational versus sequential intent.
• Parameter-width and boundary errors.
• Passing the happy path while missing reset, overflow, simultaneous operations, or illegal requests.

Interview follow-up questions

• How would you parameterize this design without introducing width or boundary bugs?
• What changes if reset timing or polarity changes?

Concepts to review

branch predictor, counter, microarchitecture

Open 2-bit Saturating Counter in the HDLForge interactive editor.

Related problems

• 2:1 Multiplexer — Easy
• Parameterized Counter — Easy
• Priority Encoder — Medium
• Synchronous FIFO — Hard
• Shift Register — Easy

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