RTL Design · Medium · Verilog, SystemVerilog, VHDL

FIFO Overflow / Underflow Sticky Flags

Record illegal FIFO access attempts.

Task

Set overflow if wr_en occurs while full. Set underflow if rd_en occurs while empty. Flags remain set until clear or reset.

Examples

• Implement the stated behavior for all legal input combinations.

Constraints

• Use synthesizable SystemVerilog.
• Do not use delays.

What this problem is testing

A strong answer translates the requirement into synthesizable state and combinational logic, states reset and update semantics precisely, and handles boundary conditions rather than only the nominal case.

Verification plan

• Check reset or initialization before normal operation.
• Exercise the nominal sequence cycle by cycle.
• Test boundaries such as zero, maximum count, wraparound, full/empty, or simultaneous controls when they apply.
• Prove the design holds state when an enable or qualifying condition is absent.

Edge cases worth testing

• Write when full and read when empty.
• Simultaneous read and write.
• Pointer wraparound and transitions into and out of full/empty.

Common mistakes

• Incomplete combinational assignments that infer a latch.
• Blocking/non-blocking assignments that do not match combinational versus sequential intent.
• Parameter-width and boundary errors.
• Passing the happy path while missing reset, overflow, simultaneous operations, or illegal requests.

Interview follow-up questions

• How would you parameterize this design without introducing width or boundary bugs?
• What changes if reset timing or polarity changes?
• How would this change for an asynchronous FIFO?

Concepts to review

fifo, overflow, underflow

Open FIFO Overflow / Underflow Sticky Flags in the HDLForge interactive editor.

Related problems

• 2:1 Multiplexer — Easy
• Parameterized Counter — Easy
• Priority Encoder — Medium
• Synchronous FIFO — Hard
• Shift Register — Easy

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