UART Receive Controller
Coordinate start-bit detection, data sampling, and byte completion.
Task
Create a receive controller that enters an active state after `start_seen`, emits one `sample` pulse for each of eight data bits on `baud_tick`, and asserts `data_valid` after the eighth sample.
Examples
- start_seen=1 → active=1
- eighth baud tick → data_valid=1 and receiver returns idle
Constraints
- Generate exactly eight sample pulses.
- `data_valid` is a one-cycle pulse.
- Ignore additional start pulses while active.
What this problem is testing
A strong answer translates the requirement into synthesizable state and combinational logic, states reset and update semantics precisely, and handles boundary conditions rather than only the nominal case.
Interview habit: before coding, state reset behavior, the state that must be stored, and the conditions that update each output.
Verification plan
- Check reset or initialization before normal operation.
- Exercise the nominal sequence cycle by cycle.
- Test boundaries such as zero, maximum count, wraparound, full/empty, or simultaneous controls when they apply.
- Prove the design holds state when an enable or qualifying condition is absent.
Edge cases worth testing
- Back-to-back frames.
- Start/stop timing and LSB-first ordering.
Common mistakes
- Incomplete combinational assignments that infer a latch.
- Blocking/non-blocking assignments that do not match combinational versus sequential intent.
- Parameter-width and boundary errors.
- Passing the happy path while missing reset, overflow, simultaneous operations, or illegal requests.
Interview follow-up questions
- How would you parameterize this design without introducing width or boundary bugs?
- What changes if reset timing or polarity changes?
Concepts to review
UART, FSM, receiver
Open UART Receive Controller in the HDLForge interactive editor.
Related problems
- 2:1 Multiplexer — Easy
- Parameterized Counter — Easy
- Priority Encoder — Medium
- Synchronous FIFO — Hard
- Shift Register — Easy
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