UART RX Data Shifter
Collect eight sampled serial data bits into a byte.
Task
On each `sample` pulse, capture the current RX bit into an 8-bit register. UART arrives LSB-first, so the first sampled data bit becomes `data_out[0]`.
Examples
- first sample rx=1 → data_out[0]=1
- eight samples reconstruct the received byte
Constraints
- Capture only when `sample` is high.
- Track which bit position is being filled.
- Reset clears the data and bit index.
What this problem is testing
A strong answer translates the requirement into synthesizable state and combinational logic, states reset and update semantics precisely, and handles boundary conditions rather than only the nominal case.
Interview habit: before coding, state reset behavior, the state that must be stored, and the conditions that update each output.
Verification plan
- Check reset or initialization before normal operation.
- Exercise the nominal sequence cycle by cycle.
- Test boundaries such as zero, maximum count, wraparound, full/empty, or simultaneous controls when they apply.
- Prove the design holds state when an enable or qualifying condition is absent.
Edge cases worth testing
- Back-to-back frames.
- Start/stop timing and LSB-first ordering.
Common mistakes
- Incomplete combinational assignments that infer a latch.
- Blocking/non-blocking assignments that do not match combinational versus sequential intent.
- Parameter-width and boundary errors.
- Passing the happy path while missing reset, overflow, simultaneous operations, or illegal requests.
Interview follow-up questions
- How would you parameterize this design without introducing width or boundary bugs?
- What changes if reset timing or polarity changes?
Concepts to review
UART, receiver, shift-register
Open UART RX Data Shifter in the HDLForge interactive editor.
Related problems
- 2:1 Multiplexer — Easy
- Parameterized Counter — Easy
- Priority Encoder — Medium
- Synchronous FIFO — Hard
- Shift Register — Easy
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