RISC-V Register File
Create the 32 × 32-bit register file with two read ports, one write port and the architectural x0 rule.
Task
Implement two combinational reads and one clocked write. Register x0 must always read as zero and ignore writes.
Examples
- rs1=0 → rs1_data=0
- rd_write=1, rd=5 → regs[5] receives rd_data on the rising edge
Constraints
- 32 registers, each 32 bits.
- Reads are combinational.
- Writes are synchronous.
- x0 is hard-wired to zero.
What this problem is testing
A strong answer translates the requirement into synthesizable state and combinational logic, states reset and update semantics precisely, and handles boundary conditions rather than only the nominal case.
Interview habit: before coding, state reset behavior, the state that must be stored, and the conditions that update each output.
Verification plan
- Check reset or initialization before normal operation.
- Exercise the nominal sequence cycle by cycle.
- Test boundaries such as zero, maximum count, wraparound, full/empty, or simultaneous controls when they apply.
- Prove the design holds state when an enable or qualifying condition is absent.
Common mistakes
- Incomplete combinational assignments that infer a latch.
- Blocking/non-blocking assignments that do not match combinational versus sequential intent.
- Parameter-width and boundary errors.
- Passing the happy path while missing reset, overflow, simultaneous operations, or illegal requests.
Interview follow-up questions
- How would you parameterize this design without introducing width or boundary bugs?
- What changes if reset timing or polarity changes?
Concepts to review
RISC-V, register-file, datapath
Open RISC-V Register File in the HDLForge interactive editor.
Related problems
- 2:1 Multiplexer — Easy
- Parameterized Counter — Easy
- Priority Encoder — Medium
- Synchronous FIFO — Hard
- Shift Register — Easy
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