DMA Write Channel
Buffer a read result and hold the write request until the destination accepts it.
Task
On load_data capture data and address and assert write_valid. Keep them stable until write_ready, then pulse accepted.
Examples
- Implement the required behavior and preserve it under the stated control conditions.
Constraints
- Use synthesizable SystemVerilog unless this stage is verification-only.
What this problem is testing
A strong answer translates the requirement into synthesizable state and combinational logic, states reset and update semantics precisely, and handles boundary conditions rather than only the nominal case.
Interview habit: before coding, state reset behavior, the state that must be stored, and the conditions that update each output.
Verification plan
- Check reset or initialization before normal operation.
- Exercise the nominal sequence cycle by cycle.
- Test boundaries such as zero, maximum count, wraparound, full/empty, or simultaneous controls when they apply.
- Prove the design holds state when an enable or qualifying condition is absent.
Common mistakes
- Incomplete combinational assignments that infer a latch.
- Blocking/non-blocking assignments that do not match combinational versus sequential intent.
- Parameter-width and boundary errors.
- Passing the happy path while missing reset, overflow, simultaneous operations, or illegal requests.
Interview follow-up questions
- How would you parameterize this design without introducing width or boundary bugs?
- What changes if reset timing or polarity changes?
Concepts to review
DMA, ready-valid, write
Open DMA Write Channel in the HDLForge interactive editor.
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