RTL Design · Medium · SystemVerilog

Synchronize Gray Pointers

Move a Gray-coded pointer safely into the opposite clock domain.

Task

Build a parameterized two-flop synchronizer for a Gray pointer. Both synchronization stages must be clocked by the destination clock.

Examples

• async_gray changes → sync_gray updates after two destination clocks

Constraints

• Use two sequential stages.
• Reset both stages to zero.
• Do not combine this with payload-data synchronization.

What this problem is testing

A strong answer translates the requirement into synthesizable state and combinational logic, states reset and update semantics precisely, and handles boundary conditions rather than only the nominal case.

Verification plan

• Check reset or initialization before normal operation.
• Exercise the nominal sequence cycle by cycle.
• Test boundaries such as zero, maximum count, wraparound, full/empty, or simultaneous controls when they apply.
• Prove the design holds state when an enable or qualifying condition is absent.

Edge cases worth testing

• A transition close to the destination clock edge.
• A pulse shorter than a destination clock period.

Common mistakes

• Incomplete combinational assignments that infer a latch.
• Blocking/non-blocking assignments that do not match combinational versus sequential intent.
• Parameter-width and boundary errors.
• Passing the happy path while missing reset, overflow, simultaneous operations, or illegal requests.

Interview follow-up questions

• How would you parameterize this design without introducing width or boundary bugs?
• What changes if reset timing or polarity changes?

Concepts to review

CDC, synchronizer, Gray-code

Open Synchronize Gray Pointers in the HDLForge interactive editor.

Related problems

• 2:1 Multiplexer — Easy
• Parameterized Counter — Easy
• Priority Encoder — Medium
• Synchronous FIFO — Hard
• Shift Register — Easy

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