RISC-V ALU
Implement the arithmetic and logic unit used by the guided RV32I core.
Task
Implement ADD, SUB, AND, OR, XOR, signed SLT, SLL, SRL and SRA in a combinational case statement.
Examples
- alu_op=0 → a+b
- alu_op=5 → signed a<b
- alu_op=8 → arithmetic right shift
Constraints
- Combinational logic only.
- Provide a safe default result.
- Use signed semantics for SLT and SRA.
What this problem is testing
A strong answer translates the requirement into synthesizable state and combinational logic, states reset and update semantics precisely, and handles boundary conditions rather than only the nominal case.
Interview habit: before coding, state reset behavior, the state that must be stored, and the conditions that update each output.
Verification plan
- Check reset or initialization before normal operation.
- Exercise the nominal sequence cycle by cycle.
- Test boundaries such as zero, maximum count, wraparound, full/empty, or simultaneous controls when they apply.
- Prove the design holds state when an enable or qualifying condition is absent.
Common mistakes
- Incomplete combinational assignments that infer a latch.
- Blocking/non-blocking assignments that do not match combinational versus sequential intent.
- Parameter-width and boundary errors.
- Passing the happy path while missing reset, overflow, simultaneous operations, or illegal requests.
Interview follow-up questions
- How would you parameterize this design without introducing width or boundary bugs?
- What changes if reset timing or polarity changes?
Concepts to review
RISC-V, ALU, datapath
Open RISC-V ALU in the HDLForge interactive editor.
Related problems
- 2:1 Multiplexer — Easy
- Parameterized Counter — Easy
- Priority Encoder — Medium
- Synchronous FIFO — Hard
- Shift Register — Easy
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