RTL Design · Medium · SystemVerilog

Branch Redirect and Flush

Redirect fetch and invalidate younger work after a taken branch.

Task

Select the next PC between sequential PC+4 and the branch target, and assert flush whenever a branch is taken.

Examples

Constraints

What this problem is testing

A strong answer translates the requirement into synthesizable state and combinational logic, states reset and update semantics precisely, and handles boundary conditions rather than only the nominal case.

Interview habit: before coding, state reset behavior, the state that must be stored, and the conditions that update each output.

Verification plan

Common mistakes

Interview follow-up questions

Concepts to review

RISC-V, branch, flush

Open Branch Redirect and Flush in the HDLForge interactive editor.

Related problems

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