RTL Design · Hard · SystemVerilog

2x3 AXI-Lite Crossbar Top

Integrate arbitration, address decode and transaction ownership for a two-master, three-slave AXI-Lite write crossbar.

Task

Choose a master, decode its AW address, expose selected_master and selected_slave, and hold selection while a write transaction is outstanding.

Examples

Constraints

What this problem is testing

A strong answer translates the requirement into synthesizable state and combinational logic, states reset and update semantics precisely, and handles boundary conditions rather than only the nominal case.

Interview habit: before coding, state reset behavior, the state that must be stored, and the conditions that update each output.

Verification plan

Common mistakes

Interview follow-up questions

Concepts to review

AXI, crossbar, integration

Open 2x3 AXI-Lite Crossbar Top in the HDLForge interactive editor.

Related problems

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