RTL Design · Medium · SystemVerilog

UART Transmit Controller

Control when a byte is loaded, shifted, and reported complete.

Task

Create the UART transmit controller. `start` begins a 10-bit frame, `baud_tick` advances one transmitted bit, `busy` remains high during the frame, and `done` pulses after the stop bit.

Examples

• start=1 while idle → load=1 and busy=1
• 10 baud ticks later → done=1 for one cycle

Constraints

• Ignore a new start request while busy.
• Count exactly 10 transmitted bits.
• `done` is a one-cycle pulse.

What this problem is testing

A strong answer translates the requirement into synthesizable state and combinational logic, states reset and update semantics precisely, and handles boundary conditions rather than only the nominal case.

Verification plan

• Check reset or initialization before normal operation.
• Exercise the nominal sequence cycle by cycle.
• Test boundaries such as zero, maximum count, wraparound, full/empty, or simultaneous controls when they apply.
• Prove the design holds state when an enable or qualifying condition is absent.

Edge cases worth testing

• Back-to-back frames.
• Start/stop timing and LSB-first ordering.

Common mistakes

• Incomplete combinational assignments that infer a latch.
• Blocking/non-blocking assignments that do not match combinational versus sequential intent.
• Parameter-width and boundary errors.
• Passing the happy path while missing reset, overflow, simultaneous operations, or illegal requests.

Interview follow-up questions

• How would you parameterize this design without introducing width or boundary bugs?
• What changes if reset timing or polarity changes?

Concepts to review

UART, FSM, control

Open UART Transmit Controller in the HDLForge interactive editor.

Related problems

• 2:1 Multiplexer — Easy
• Parameterized Counter — Easy
• Priority Encoder — Medium
• Synchronous FIFO — Hard
• Shift Register — Easy

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