ID/EX Pipeline Register
Carry decoded operands and control signals into the execute stage.
Task
Register source operands, immediate, destination register and writeback controls. A bubble must clear side-effect controls.
Examples
- bubble=1 disables register write and memory read/write.
- Normal cycle captures operands and control.
Constraints
- Use nonblocking assignments.
- Bubble must suppress side effects.
- Retain `rd`, operands and immediate on normal capture.
What this problem is testing
A strong answer translates the requirement into synthesizable state and combinational logic, states reset and update semantics precisely, and handles boundary conditions rather than only the nominal case.
Interview habit: before coding, state reset behavior, the state that must be stored, and the conditions that update each output.
Verification plan
- Check reset or initialization before normal operation.
- Exercise the nominal sequence cycle by cycle.
- Test boundaries such as zero, maximum count, wraparound, full/empty, or simultaneous controls when they apply.
- Prove the design holds state when an enable or qualifying condition is absent.
Edge cases worth testing
- An immediately preceding dependency.
- A dependency that can be forwarded versus one that requires a stall.
Common mistakes
- Incomplete combinational assignments that infer a latch.
- Blocking/non-blocking assignments that do not match combinational versus sequential intent.
- Parameter-width and boundary errors.
- Passing the happy path while missing reset, overflow, simultaneous operations, or illegal requests.
Interview follow-up questions
- How would you parameterize this design without introducing width or boundary bugs?
- What changes if reset timing or polarity changes?
Concepts to review
RISC-V, pipeline, ID/EX
Open ID/EX Pipeline Register in the HDLForge interactive editor.
Related problems
- 2:1 Multiplexer — Easy
- Parameterized Counter — Easy
- Priority Encoder — Medium
- Synchronous FIFO — Hard
- Shift Register — Easy
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