Memory-Mapped I²C Register Slave
Integrate a simplified I²C register peripheral with address matching, ACK generation, register writes and sequential register reads.
Task
Use 7-bit address SLAVE_ADDR. After START, receive address+R/W and ACK matches. In write mode, the first data byte loads reg_ptr and following bytes write regs[reg_ptr] with auto-increment. In read mode, present regs[reg_ptr] on tx_data, pulse tx_load, and advance to the next register when read_next is asserted. STOP returns to idle.
Examples
- Implement the required protocol behavior and preserve it across the stated timing/control conditions.
Constraints
- Use synthesizable SystemVerilog and synchronous state/control logic unless the task explicitly requires edge detection or open-drain behavior.
What this problem is testing
A strong answer translates the requirement into synthesizable state and combinational logic, states reset and update semantics precisely, and handles boundary conditions rather than only the nominal case.
Verification plan
- Check reset or initialization before normal operation.
- Exercise the nominal sequence cycle by cycle.
- Test boundaries such as zero, maximum count, wraparound, full/empty, or simultaneous controls when they apply.
- Prove the design holds state when an enable or qualifying condition is absent.
Common mistakes
- Incomplete combinational assignments that infer a latch.
- Blocking/non-blocking assignments that do not match combinational versus sequential intent.
- Parameter-width and boundary errors.
- Passing the happy path while missing reset, overflow, simultaneous operations, or illegal requests.
Interview follow-up questions
- How would you parameterize this design without introducing width or boundary bugs?
- What changes if reset timing or polarity changes?
Concepts to review
I2C, slave, register peripheral
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Related problems
- 2:1 Multiplexer — Easy
- Parameterized Counter — Easy
- Priority Encoder — Medium
- Synchronous FIFO — Hard
- Shift Register — Easy
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