UVM · Medium · SystemVerilog

AXI Crossbar Sequence Item

Represent one AXI-Lite write request including source master and target address.

Task

Create a UVM sequence item with randomized master_id, addr and data plus observed resp.

Examples

Constraints

What this problem is testing

UVM interview problems test transaction flow, ownership, phasing, TLM connections, checking strategy, and whether components remain reusable and debuggable.

Interview habit: before coding, state reset behavior, the state that must be stored, and the conditions that update each output.

Verification plan

Common mistakes

Interview follow-up questions

Concepts to review

UVM, AXI, transaction

Open AXI Crossbar Sequence Item in the HDLForge interactive editor.

Related problems

Explore the UVM Practice & Interview Preparation hub.

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