UVM · Hard · SystemVerilog

Crossbar Contention Sequence

Create sustained contention so both masters repeatedly target the same slave.

Task

Generate 50 paired writes to slave 1's address region, alternating master_id between 0 and 1.

Examples

Constraints

What this problem is testing

UVM interview problems test transaction flow, ownership, phasing, TLM connections, checking strategy, and whether components remain reusable and debuggable.

Interview habit: before coding, state reset behavior, the state that must be stored, and the conditions that update each output.

Verification plan

Common mistakes

Interview follow-up questions

Concepts to review

UVM, arbitration, contention

Open Crossbar Contention Sequence in the HDLForge interactive editor.

Related problems

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