always_comb vs always_ff
Identify the correct procedural blocks for combinational and sequential logic.
Task
Rewrite a small RTL fragment using idiomatic SystemVerilog constructs.
Examples
- Combinational next-state logic → always_comb
- Flip-flop state update → always_ff
Constraints
- Use SystemVerilog.
- Avoid incomplete combinational assignments.
What this problem is testing
The interviewer is usually testing language semantics as much as syntax: driver intent, scheduling, type behavior, interface directionality, and whether the construct communicates hardware intent clearly.
Interview habit: before coding, state reset behavior, the state that must be stored, and the conditions that update each output.
Verification plan
- Compile with warnings enabled and investigate multiple drivers or incomplete assignments.
- Exercise values that expose signedness, width extension, packed-array indexing, or modport direction mistakes.
- Check behavior around clock edges and time zero.
- Compare the construct with its simpler Verilog equivalent to confirm the intended hardware behavior.
Common mistakes
- Using a construct without understanding its scheduling or driver rules.
- Mixing signed and unsigned arithmetic accidentally.
- Confusing packed and unpacked dimensions.
- Hiding signal ownership with unclear interface or modport directions.
Interview follow-up questions
- What language rule makes this construct safer or clearer than the equivalent Verilog?
- What simulation/synthesis mismatch could appear if this were written carelessly?
Concepts to review
syntax, rtl
Open always_comb vs always_ff in the HDLForge interactive editor.
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