Accelerators · Medium · Verilog, SystemVerilog, VHDL

Four-Lane Signed Vector Maximum

Implement a four-lane signed max-reduction datapath.

Task

Return the greatest signed 16-bit value among x0, x1, x2 and x3.

Examples

• [1,9,3,4] -> 9
• [-7,-2,-9,-4] -> -2

Constraints

• Inputs and output are signed 16-bit.
• Purely combinational RTL.

Accelerator verification checklist

• Exercise zero, maximum positive and negative operands where signed data is used.
• Check exact bit growth and make overflow or saturation behavior intentional.
• Verify reset, enable, valid and pipeline alignment cycle by cycle.
• Send back-to-back data to confirm the advertised throughput.

Concepts to review

accelerator, vector, reduction, signed

Open Four-Lane Signed Vector Maximum in the HDLForge interactive editor.

Related problems

• Signed INT8 Multiply-Accumulate — Easy
• Four-Lane INT8 Dot Product — Medium
• Eight-Lane Reduction Adder — Medium
• ReLU with 8-bit Saturation — Medium
• Systolic Array Processing Element — Hard