Matrix Compute Controller
Sequence input acceptance, one compute phase and output availability.
Task
Implement IDLE, COMPUTE and DONE states. `start` leaves IDLE, COMPUTE lasts one cycle for a fully parallel 2x2 datapath, and DONE holds `out_valid` until `out_ready`.
Examples
- start in IDLE → COMPUTE.
- COMPUTE → DONE.
- DONE + out_ready → IDLE.
Constraints
- Use an enumerated state type.
- Expose `busy` during COMPUTE.
- Hold `out_valid` during backpressure.
Accelerator verification checklist
- Exercise zero, maximum positive and negative operands where signed data is used.
- Check exact bit growth and make overflow or saturation behavior intentional.
- Verify reset, enable, valid and pipeline alignment cycle by cycle.
- Send back-to-back data to confirm the advertised throughput.
Concepts to review
matrix multiply, FSM, control
Open Matrix Compute Controller in the HDLForge interactive editor.
Related problems
- Signed INT8 Multiply-Accumulate — Easy
- Four-Lane INT8 Dot Product — Medium
- Eight-Lane Reduction Adder — Medium
- ReLU with 8-bit Saturation — Medium
- Systolic Array Processing Element — Hard