Convolution Valid Pipeline
Align output validity with a three-stage convolution datapath.
Task
Delay in_valid by three cycles using a shift register and clear the pipeline on reset.
Examples
- Complete the required behavior and preserve it under the stated control conditions.
Constraints
- Use synthesizable SystemVerilog unless this is a verification-only stage.
Accelerator verification checklist
- Exercise zero, maximum positive and negative operands where signed data is used.
- Check exact bit growth and make overflow or saturation behavior intentional.
- Verify reset, enable, valid and pipeline alignment cycle by cycle.
- Send back-to-back data to confirm the advertised throughput.
Concepts to review
convolution, pipeline, valid
Open Convolution Valid Pipeline in the HDLForge interactive editor.
Related problems
- Signed INT8 Multiply-Accumulate — Easy
- Four-Lane INT8 Dot Product — Medium
- Eight-Lane Reduction Adder — Medium
- ReLU with 8-bit Saturation — Medium
- Systolic Array Processing Element — Hard