Accelerators · Hard · Verilog, SystemVerilog, VHDL

Valid-Ready Streaming Accumulator

Build a streaming accumulator that updates only on successful ready/valid transfers.

Task

Whenever in_valid && in_ready is true, add signed in_data to acc. clear synchronously resets the accumulator. This sink is always ready when not in reset.

Examples

• valid sample 3 then -1 -> acc=2
• in_valid=0 -> accumulator holds

Constraints

• 16-bit signed input and 32-bit signed accumulator.
• Synchronous active-high reset.
• in_ready is deasserted during reset.

Accelerator verification checklist

• Exercise zero, maximum positive and negative operands where signed data is used.
• Check exact bit growth and make overflow or saturation behavior intentional.
• Verify reset, enable, valid and pipeline alignment cycle by cycle.
• Send back-to-back data to confirm the advertised throughput.

Concepts to review

accelerator, streaming, ready-valid, accumulator

Open Valid-Ready Streaming Accumulator in the HDLForge interactive editor.

Related problems

• Signed INT8 Multiply-Accumulate — Easy
• Four-Lane INT8 Dot Product — Medium
• Eight-Lane Reduction Adder — Medium
• ReLU with 8-bit Saturation — Medium
• Systolic Array Processing Element — Hard