Accelerators · Medium · Verilog, SystemVerilog, VHDL

Three-Tap INT8 Convolution

Create the arithmetic core of a small 1D convolution engine.

Task

Compute signed x0*k0 + x1*k1 + x2*k2 combinationally using signed INT8 operands.

Examples

• [1,2,3] with [1,1,1] -> 6
• [-1,2,-3] with [2,3,4] -> -8

Constraints

• All operands are signed 8-bit.
• Use a signed 18-bit output.
• Combinational RTL.

Accelerator verification checklist

• Exercise zero, maximum positive and negative operands where signed data is used.
• Check exact bit growth and make overflow or saturation behavior intentional.
• Verify reset, enable, valid and pipeline alignment cycle by cycle.
• Send back-to-back data to confirm the advertised throughput.

Concepts to review

accelerator, convolution, dot-product, int8

Open Three-Tap INT8 Convolution in the HDLForge interactive editor.

Related problems

• Signed INT8 Multiply-Accumulate — Easy
• Four-Lane INT8 Dot Product — Medium
• Eight-Lane Reduction Adder — Medium
• ReLU with 8-bit Saturation — Medium
• Systolic Array Processing Element — Hard