Simulation Timeout Watchdog
Prevent a hung test from running forever.
Task
Fork the main test and a watchdog. The watchdog must call $fatal if done is not observed within 1000 clock cycles.
Examples
- Implement the requested verification structure or behavior.
Constraints
- Use SystemVerilog.
- Keep the code focused on the requested verification concept.
What this problem is testing
The interviewer is usually testing language semantics as much as syntax: driver intent, scheduling, type behavior, interface directionality, and whether the construct communicates hardware intent clearly.
Interview habit: before coding, state reset behavior, the state that must be stored, and the conditions that update each output.
Verification plan
- Compile with warnings enabled and investigate multiple drivers or incomplete assignments.
- Exercise values that expose signedness, width extension, packed-array indexing, or modport direction mistakes.
- Check behavior around clock edges and time zero.
- Compare the construct with its simpler Verilog equivalent to confirm the intended hardware behavior.
Common mistakes
- Using a construct without understanding its scheduling or driver rules.
- Mixing signed and unsigned arithmetic accidentally.
- Confusing packed and unpacked dimensions.
- Hiding signal ownership with unclear interface or modport directions.
Interview follow-up questions
- What language rule makes this construct safer or clearer than the equivalent Verilog?
- What simulation/synthesis mismatch could appear if this were written carelessly?
Concepts to review
testbench, timeout, watchdog
Open Simulation Timeout Watchdog in the HDLForge interactive editor.
Related problems
- always_comb vs always_ff — Easy
- SystemVerilog Interface — Medium
- Timeout and Retry FSM — Hard
- Clock and Reset Generator — Easy
- Reusable Stimulus Task — Easy
Explore the SystemVerilog Practice & Interview Preparation hub.