HDLForge structured practice path

FPGA Practice Problems

This path emphasizes the difference between RTL that merely simulates and RTL that behaves predictably on an FPGA. It mixes logic design with CDC, reset and interface considerations.

How to use this practice path

Stage 1
Solve the RTL function first.
Stage 2
Identify asynchronous inputs and clock-domain boundaries.
Stage 3
Consider reset release and inferred FPGA resources.
Stage 4
Check protocol timing and implementation assumptions.

Problems to solve

01 · FPGA · Easy
Button Debouncer
Create a synchronous button debouncer suitable for an FPGA.02 · FPGA · Easy
Traffic Light FSM
Design a finite-state machine controlling a simple traffic light sequence.03 · FPGA · Easy
Parameterized PWM Generator
Generate a PWM waveform from an unsigned duty-cycle input.04 · FPGA · Easy
Clock-Enable Data Register
Model the FPGA-friendly alternative to fabric clock gating: a register controlled by clock enable.05 · RTL Design · Easy
Async FIFO Dual-Port Memory
Create storage that can be written and read from different clock domains.06 · FPGA · Easy
Four-Sample Delay Line
Store the current and previous input samples for a four-tap FIR.07 · FPGA · Easy
DSP Valid Pipeline
Keep control timing aligned with a multi-stage arithmetic datapath.08 · FPGA · Easy
Streaming Byte Position Counter
Track byte position within a packet without buffering the complete frame.09 · FPGA · Easy
Packet Statistics Counters
Maintain simple line-rate counters for total IPv4 packets and UDP packets.10 · FPGA · Easy
Feed Word Counter
Track 32-bit word position inside each market-data message.11 · FPGA · Easy
Message Classifier
Classify three feed message types into add, update and delete operations.12 · FPGA · Easy
SPI Clock Divider
Generate a programmable SPI clock-enable tick from the system clock.13 · FPGA · Easy
SPI Chip-Select Controller
Control an active-low SPI chip-select around a transfer.14 · RTL Design · Medium
Small Register File
Implement a 4-entry register file with one synchronous write port and two asynchronous read ports.15 · RTL Design · Medium
Programmable Clock Divider
Create a programmable divide-by-N toggle output.16 · Protocols · Medium
UART Transmitter
Design an 8-N-1 UART transmitter.17 · RTL Design · Medium
Simple Dual-Port RAM
Infer a small synchronous-write, asynchronous-read dual-port memory.18 · Protocols · Medium
Backpressure-Safe Ready/Valid Source
Implement a source register that obeys ready/valid protocol semantics.

Interview routine

For each problem, first restate the requirement and assumptions. Then write the RTL, assertion, verification component or architecture derivation without looking at a solution. Before running anything, list at least three edge cases. Finish by explaining how you would verify the result and what trade-offs you made.

Keep going

Use the interactive HDLForge problem workspace, browse company-style tracks, or choose a hardware project that uses the same skills.

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