CPU / GPU Hardware
Develop processor-oriented RTL skills around register structures, pipelines, memories, arbitration and compute datapaths.
Practice problems
Use these exercises to build the core implementation and verification skills for this path.
Small Register File
Implement a 4-entry register file with one synchronous write port and two asynchronous read ports.Elastic Pipeline Register
Implement a single-stage pipeline register with an aligned valid bit.Ready/Valid Skid Buffer
Build a one-entry skid buffer that preserves data when downstream backpressure arrives.Simple Dual-Port RAM
Infer a small synchronous-write, asynchronous-read dual-port memory.Synchronous FIFO
Implement a synchronous parameterized FIFO with ready/valid-style enqueue and dequeue controls.4-Request Priority Arbiter
A priority arbiter chooses one winner when multiple devices request access to a shared resource at the same time.Backpressure-Safe Ready/Valid Source
Implement a source register that obeys ready/valid protocol semantics.AXI-Lite Write Register Slave
Implement the write side of a single-register AXI-Lite slave.Four-Lane Signed Vector Maximum
Implement a four-lane signed max-reduction datapath.2x2 Matrix Multiply Datapath
Implement a small combinational 2x2 signed matrix-multiply datapath.
Implement a 4-entry register file with one synchronous write port and two asynchronous read ports.Elastic Pipeline Register
Implement a single-stage pipeline register with an aligned valid bit.Ready/Valid Skid Buffer
Build a one-entry skid buffer that preserves data when downstream backpressure arrives.Simple Dual-Port RAM
Infer a small synchronous-write, asynchronous-read dual-port memory.Synchronous FIFO
Implement a synchronous parameterized FIFO with ready/valid-style enqueue and dequeue controls.4-Request Priority Arbiter
A priority arbiter chooses one winner when multiple devices request access to a shared resource at the same time.Backpressure-Safe Ready/Valid Source
Implement a source register that obeys ready/valid protocol semantics.AXI-Lite Write Register Slave
Implement the write side of a single-register AXI-Lite slave.Four-Lane Signed Vector Maximum
Implement a four-lane signed max-reduction datapath.2x2 Matrix Multiply Datapath
Implement a small combinational 2x2 signed matrix-multiply datapath.
Projects for this path
Use the projects to combine individual skills into larger portfolio-ready systems.
32-bit RISC-V CPU
Build a complete RV32I datapath one block at a time before moving into pipelining and processor microarchitecture.Three-Stage Pipelined RISC-V Core
Move beyond a basic CPU by implementing pipeline state, forwarding, load-use stalls, branch flushes and writeback control.Branch Predictor
Build the prediction structures behind speculative fetch: saturating counters, a PC-indexed BHT, BTB lookup, next-PC selection and recovery.SIMD / Vector Execution Unit
Build a four-lane vector execution block with arithmetic lanes, masking, reductions, architectural vector registers and pipelined output.Cache / Memory Controller
Build a direct-mapped cache from address decode and tag/data storage through dirty writeback, refill sequencing and controller integration.Small RISC-V SoC
Integrate processor-facing ROM, RAM, GPIO, timer, interrupts and memory-mapped response routing into a compact programmable SoC.RISC-V Core Verification
Verify architectural retirement with constrained-random instructions, a reference model, scoreboarding, assertions and functional coverage.
Open the interactive CPU / GPU Hardware roadmapBuild a complete RV32I datapath one block at a time before moving into pipelining and processor microarchitecture.Three-Stage Pipelined RISC-V Core
Move beyond a basic CPU by implementing pipeline state, forwarding, load-use stalls, branch flushes and writeback control.Branch Predictor
Build the prediction structures behind speculative fetch: saturating counters, a PC-indexed BHT, BTB lookup, next-PC selection and recovery.SIMD / Vector Execution Unit
Build a four-lane vector execution block with arithmetic lanes, masking, reductions, architectural vector registers and pipelined output.Cache / Memory Controller
Build a direct-mapped cache from address decode and tag/data storage through dirty writeback, refill sequencing and controller integration.Small RISC-V SoC
Integrate processor-facing ROM, RAM, GPIO, timer, interrupts and memory-mapped response routing into a compact programmable SoC.RISC-V Core Verification
Verify architectural retirement with constrained-random instructions, a reference model, scoreboarding, assertions and functional coverage.