Jane Street FPGA & Hardware Interview Practice
Low-latency RTL, deterministic pipelines, arbitration, FIFOs, architecture reasoning and performance-aware FPGA design.
Independent preparation resource: HDLForge is not affiliated with Jane Street. These are practice problems selected for relevant hardware skills; they are not presented as leaked or guaranteed interview questions.
What to practise
Low-latency RTL, arbitration, backpressure, streaming pipelines and deterministic datapaths.
Practice set
Work through these problems without looking at solutions first. Explain assumptions, edge cases and verification strategy as if an interviewer were reviewing the design.
4-Request Priority Arbiter
A priority arbiter chooses one winner when multiple devices request access to a shared resource at the same time.Ready/Valid Skid Buffer
Build a one-entry skid buffer that preserves data when downstream backpressure arrives.Synchronous FIFO
Implement a synchronous parameterized FIFO with ready/valid-style enqueue and dequeue controls.Elastic Pipeline Register
Implement a single-stage pipeline register with an aligned valid bit.Backpressure-Safe Ready/Valid Source
Implement a source register that obeys ready/valid protocol semantics.Small Register File
Implement a 4-entry register file with one synchronous write port and two asynchronous read ports.Toggle-Based Pulse Synchronizer
Transfer a one-cycle pulse between unrelated clock domains using a toggle synchronizer.Valid-Tagged Pipelined Multiplier
Implement a one-cycle-latency signed multiplier with an aligned valid signal, a common accelerator pipeline building block.Valid-Ready Streaming Accumulator
Build a streaming accumulator that updates only on successful ready/valid transfers.One-Hot Traffic-Light FSM
Implement a three-state one-hot finite-state machine.
A priority arbiter chooses one winner when multiple devices request access to a shared resource at the same time.Ready/Valid Skid Buffer
Build a one-entry skid buffer that preserves data when downstream backpressure arrives.Synchronous FIFO
Implement a synchronous parameterized FIFO with ready/valid-style enqueue and dequeue controls.Elastic Pipeline Register
Implement a single-stage pipeline register with an aligned valid bit.Backpressure-Safe Ready/Valid Source
Implement a source register that obeys ready/valid protocol semantics.Small Register File
Implement a 4-entry register file with one synchronous write port and two asynchronous read ports.Toggle-Based Pulse Synchronizer
Transfer a one-cycle pulse between unrelated clock domains using a toggle synchronizer.Valid-Tagged Pipelined Multiplier
Implement a one-cycle-latency signed multiplier with an aligned valid signal, a common accelerator pipeline building block.Valid-Ready Streaming Accumulator
Build a streaming accumulator that updates only on successful ready/valid transfers.One-Hot Traffic-Light FSM
Implement a three-state one-hot finite-state machine.
Recommended projects
Projects give you deeper material to discuss after the shorter interview exercises.
Low-Latency Market Data Parser
Shows the design style used for deterministic, line-rate FPGA processing without claiming any specific firm uses the exact design.Timestamped Feed-to-Action Pipeline
Makes latency engineering measurable and gives you a strong artifact to discuss in FPGA/HFT interviews.FPGA Packet Parser and Statistics Engine
Shows high-throughput datapath design and implementation awareness.
Shows the design style used for deterministic, line-rate FPGA processing without claiming any specific firm uses the exact design.Timestamped Feed-to-Action Pipeline
Makes latency engineering measurable and gives you a strong artifact to discuss in FPGA/HFT interviews.FPGA Packet Parser and Statistics Engine
Shows high-throughput datapath design and implementation awareness.
How to use this track
- Start with the RTL and architecture problems to identify weak fundamentals.
- Repeat the set under time pressure and explain your reasoning aloud.
- For every RTL answer, state reset behavior, edge cases and how you would verify it.
- Build one related project deeply enough to discuss architecture, bugs, verification and trade-offs.