RTL Design Engineer
Build the core digital-design skills used in RTL interviews and day-to-day block design: combinational logic, state, memories, FIFOs, pipelining, CDC and clean synthesizable interfaces.
Core skills
Practice problems
Use these exercises to build the core implementation and verification skills for this path.
2:1 Multiplexer
Design a synthesizable 2:1 multiplexer.Parameterized Counter
Build a parameterized synchronous up-counter with reset.Priority Encoder
Design an 8-to-3 priority encoder where bit 7 has the highest priority.Synchronous FIFO
Implement a synchronous parameterized FIFO with ready/valid-style enqueue and dequeue controls.Shift Register
Build a parameterized register that stores multiple bits and can shift its contents by one position on each clock edge.Rising Edge Detector
Generate a one-cycle pulse whenever an input signal transitions from 0 to 1.4-Request Priority Arbiter
A priority arbiter chooses one winner when multiple devices request access to a shared resource at the same time.Small Register File
Implement a 4-entry register file with one synchronous write port and two asynchronous read ports.Programmable Clock Divider
Create a programmable divide-by-N toggle output.Ready/Valid Skid Buffer
Build a one-entry skid buffer that preserves data when downstream backpressure arrives.Elastic Pipeline Register
Implement a single-stage pipeline register with an aligned valid bit.Asynchronous-Assert Reset Synchronizer
Create a two-flop reset synchronizer with asynchronous assertion and synchronous deassertion.Binary to Gray Counter
Build a parameterized binary counter and expose its Gray-code representation.Simple Dual-Port RAM
Infer a small synchronous-write, asynchronous-read dual-port memory.One-Hot Traffic-Light FSM
Implement a three-state one-hot finite-state machine.
Design a synthesizable 2:1 multiplexer.Parameterized Counter
Build a parameterized synchronous up-counter with reset.Priority Encoder
Design an 8-to-3 priority encoder where bit 7 has the highest priority.Synchronous FIFO
Implement a synchronous parameterized FIFO with ready/valid-style enqueue and dequeue controls.Shift Register
Build a parameterized register that stores multiple bits and can shift its contents by one position on each clock edge.Rising Edge Detector
Generate a one-cycle pulse whenever an input signal transitions from 0 to 1.4-Request Priority Arbiter
A priority arbiter chooses one winner when multiple devices request access to a shared resource at the same time.Small Register File
Implement a 4-entry register file with one synchronous write port and two asynchronous read ports.Programmable Clock Divider
Create a programmable divide-by-N toggle output.Ready/Valid Skid Buffer
Build a one-entry skid buffer that preserves data when downstream backpressure arrives.Elastic Pipeline Register
Implement a single-stage pipeline register with an aligned valid bit.Asynchronous-Assert Reset Synchronizer
Create a two-flop reset synchronizer with asynchronous assertion and synchronous deassertion.Binary to Gray Counter
Build a parameterized binary counter and expose its Gray-code representation.Simple Dual-Port RAM
Infer a small synchronous-write, asynchronous-read dual-port memory.One-Hot Traffic-Light FSM
Implement a three-state one-hot finite-state machine.
Projects for this path
Use the projects to combine individual skills into larger portfolio-ready systems.
AXI4-Lite Slave Peripheral
Build a realistic memory-mapped RTL peripheral with independent AXI-Lite channels and correct response handling.Asynchronous FIFO / CDC
Build the Gray-pointer, synchronizer and full/empty logic behind a production-style dual-clock FIFO.32-bit RISC-V CPU
Build a complete RV32I datapath one block at a time before moving into pipelining and processor microarchitecture.Cache / Memory Controller
Build a direct-mapped cache from address decode and tag/data storage through dirty writeback, refill sequencing and controller integration.AXI4 Interconnect / Crossbar
Build a two-master, three-slave interconnect with address decoding, fair arbitration, ownership locking, response routing and DECERR handling.AXI-Lite to APB Bridge
A realistic SoC integration block that exercises protocol and control-path reasoning.DMA Engine
Build the data-movement engine accelerators need: programmable registers, source/destination sequencing, backpressure, transfer counting and completion interrupts.Small RISC-V SoC
Integrate processor-facing ROM, RAM, GPIO, timer, interrupts and memory-mapped response routing into a compact programmable SoC.CDC-Safe Asynchronous FIFO
Demonstrates practical clock-domain-crossing knowledge expected in many digital design roles.
Open the interactive RTL Design Engineer roadmapBuild a realistic memory-mapped RTL peripheral with independent AXI-Lite channels and correct response handling.Asynchronous FIFO / CDC
Build the Gray-pointer, synchronizer and full/empty logic behind a production-style dual-clock FIFO.32-bit RISC-V CPU
Build a complete RV32I datapath one block at a time before moving into pipelining and processor microarchitecture.Cache / Memory Controller
Build a direct-mapped cache from address decode and tag/data storage through dirty writeback, refill sequencing and controller integration.AXI4 Interconnect / Crossbar
Build a two-master, three-slave interconnect with address decoding, fair arbitration, ownership locking, response routing and DECERR handling.AXI-Lite to APB Bridge
A realistic SoC integration block that exercises protocol and control-path reasoning.DMA Engine
Build the data-movement engine accelerators need: programmable registers, source/destination sequencing, backpressure, transfer counting and completion interrupts.Small RISC-V SoC
Integrate processor-facing ROM, RAM, GPIO, timer, interrupts and memory-mapped response routing into a compact programmable SoC.CDC-Safe Asynchronous FIFO
Demonstrates practical clock-domain-crossing knowledge expected in many digital design roles.