Verilog Practice Problems
This path is for hands-on Verilog practice. The selected problems are all implementable as synthesizable RTL and progress from small coding exercises toward interview-sized blocks.
How to use this practice path
Stage 1
Write simple combinational modules without inferred latches.
Write simple combinational modules without inferred latches.
Stage 2
Practice clocked state, reset behavior and parameterization.
Practice clocked state, reset behavior and parameterization.
Stage 3
Implement stateful blocks such as FIFOs, register files and serial controllers.
Implement stateful blocks such as FIFOs, register files and serial controllers.
Stage 4
Review edge cases before opening the simulator.
Review edge cases before opening the simulator.
Problems to solve
2:1 Multiplexer
Design a synthesizable 2:1 multiplexer.
Parameterized Counter
Build a parameterized synchronous up-counter with reset.
Shift Register
Build a parameterized register that stores multiple bits and can shift its contents by one position on each clock edge.
Rising Edge Detector
Generate a one-cycle pulse whenever an input signal transitions from 0 to 1.
Button Debouncer
Create a synchronous button debouncer suitable for an FPGA.
Traffic Light FSM
Design a finite-state machine controlling a simple traffic light sequence.
Signed INT8 Multiply-Accumulate
Build the basic signed INT8 multiply-accumulate datapath used in DSP and machine-learning accelerators.
Parameterized PWM Generator
Generate a PWM waveform from an unsigned duty-cycle input.
Clock-Enable Data Register
Model the FPGA-friendly alternative to fabric clock gating: a register controlled by clock enable.
3-to-8 Decoder
Decode a 3-bit input into a one-hot 8-bit output.
16-bit Magnitude Comparator
Compare two unsigned 16-bit values.
Even-Parity Generator
Generate the parity bit required to make an 8-bit word have even parity.
Register with Clock Enable
Build an 8-bit register that updates only when enable is high.
Toggle Flip-Flop
Toggle an output bit whenever toggle_en is asserted.
Sticky Status Flag
Latch an event until software explicitly clears it.
Start/Busy/Done Controller
Implement a standard operation-control shell with start, busy and one-cycle done.
Priority Encoder
Design an 8-to-3 priority encoder where bit 7 has the highest priority.
4-Request Priority Arbiter
A priority arbiter chooses one winner when multiple devices request access to a shared resource at the same time.
Small Register File
Implement a 4-entry register file with one synchronous write port and two asynchronous read ports.
8-bit LFSR
Implement an 8-bit linear-feedback shift register for pseudo-random sequence generation.
Interview routine
For each problem, first restate the requirement and assumptions. Then write the RTL, assertion, verification component or architecture derivation without looking at a solution. Before running anything, list at least three edge cases. Finish by explaining how you would verify the result and what trade-offs you made.
Keep going
Use the interactive HDLForge problem workspace, browse company-style tracks, or choose a hardware project that uses the same skills.