HDLForge structured practice path

Digital Protocol Practice Problems

Protocol interviews are cycle-accurate. Use this path to practise framing, channel independence, backpressure, data stability and legal transaction sequencing.

How to use this practice path

Stage 1
Write the legal transfer rule in one sentence.
Stage 2
Draw the fastest and slowest valid transaction.
Stage 3
Check what must remain stable under backpressure.
Stage 4
Test back-to-back transfers and transaction boundaries.

Problems to solve

01 · RTL Design · Easy
UART Baud Tick Generator
Create the timing pulse that advances the UART transmitter and receiver.02 · RTL Design · Easy
UART TX Frame Shifter
Build the shift register that serializes a UART frame.03 · RTL Design · Easy
UART RX Start-Bit Detector
Detect the beginning of an incoming UART frame.04 · FPGA · Easy
SPI Clock Divider
Generate a programmable SPI clock-enable tick from the system clock.05 · FPGA · Easy
SPI Chip-Select Controller
Control an active-low SPI chip-select around a transfer.06 · RTL Design · Easy
I²C Address Matcher
Decode the first I²C byte into a 7-bit address and R/W bit.07 · RTL Design · Easy
I²C Clock-Stretch Control
Model clock stretching as an open-drain SCL request.08 · SVA · Medium
Valid Must Eventually Handshake
Write an assertion for a ready/valid interface.09 · Protocols · Medium
UART Transmitter
Design an 8-N-1 UART transmitter.10 · Protocols · Medium
Backpressure-Safe Ready/Valid Source
Implement a source register that obeys ready/valid protocol semantics.11 · RTL Design · Medium
Request/Acknowledge Controller
Control a request/acknowledge transaction.12 · RTL Design · Medium
UART Transmit Controller
Control when a byte is loaded, shifted, and reported complete.13 · RTL Design · Medium
UART RX Data Shifter
Collect eight sampled serial data bits into a byte.14 · RTL Design · Medium
UART Receive Controller
Coordinate start-bit detection, data sampling, and byte completion.15 · RTL Design · Medium
AXI-Lite AW Channel Capture
Accept the write address independently from write data.16 · RTL Design · Medium
AXI-Lite W Channel Capture
Accept write data independently from the write address.17 · RTL Design · Medium
AXI-Lite B Response Channel
Return one write response and hold it until the master accepts it.18 · RTL Design · Medium
AXI-Lite AR Channel Capture
Accept one AXI-Lite read address and preserve it while the read response is prepared.

Interview routine

For each problem, first restate the requirement and assumptions. Then write the RTL, assertion, verification component or architecture derivation without looking at a solution. Before running anything, list at least three edge cases. Finish by explaining how you would verify the result and what trade-offs you made.

Keep going

Use the interactive HDLForge problem workspace, browse company-style tracks, or choose a hardware project that uses the same skills.

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