FPGA Engineer
Focus on deterministic RTL, streaming datapaths, clock-domain control and board-relevant interfaces.
Practice problems
Use these exercises to build the core implementation and verification skills for this path.
Ready/Valid Skid Buffer
Build a one-entry skid buffer that preserves data when downstream backpressure arrives.Elastic Pipeline Register
Implement a single-stage pipeline register with an aligned valid bit.Backpressure-Safe Ready/Valid Source
Implement a source register that obeys ready/valid protocol semantics.Synchronous FIFO
Implement a synchronous parameterized FIFO with ready/valid-style enqueue and dequeue controls.Rising Edge Detector
Generate a one-cycle pulse whenever an input signal transitions from 0 to 1.Toggle-Based Pulse Synchronizer
Transfer a one-cycle pulse between unrelated clock domains using a toggle synchronizer.Clock-Enable Data Register
Model the FPGA-friendly alternative to fabric clock gating: a register controlled by clock enable.Valid-Tagged Pipelined Multiplier
Implement a one-cycle-latency signed multiplier with an aligned valid signal, a common accelerator pipeline building block.Valid-Ready Streaming Accumulator
Build a streaming accumulator that updates only on successful ready/valid transfers.
Build a one-entry skid buffer that preserves data when downstream backpressure arrives.Elastic Pipeline Register
Implement a single-stage pipeline register with an aligned valid bit.Backpressure-Safe Ready/Valid Source
Implement a source register that obeys ready/valid protocol semantics.Synchronous FIFO
Implement a synchronous parameterized FIFO with ready/valid-style enqueue and dequeue controls.Rising Edge Detector
Generate a one-cycle pulse whenever an input signal transitions from 0 to 1.Toggle-Based Pulse Synchronizer
Transfer a one-cycle pulse between unrelated clock domains using a toggle synchronizer.Clock-Enable Data Register
Model the FPGA-friendly alternative to fabric clock gating: a register controlled by clock enable.Valid-Tagged Pipelined Multiplier
Implement a one-cycle-latency signed multiplier with an aligned valid signal, a common accelerator pipeline building block.Valid-Ready Streaming Accumulator
Build a streaming accumulator that updates only on successful ready/valid transfers.
Projects for this path
Use the projects to combine individual skills into larger portfolio-ready systems.
SPI Controller
Build a configurable SPI master from clock generation and edge timing through MOSI/MISO shifting, chip-select control and complete multi-mode transfers.UART Controller
Build a complete serial controller from timing generation through transmit, receive and loopback integration.Hardware DSP Pipeline
Build a streaming FIR-style datapath with signed MAC arithmetic, sample history, control alignment and saturation.Asynchronous FIFO / CDC
Build the Gray-pointer, synchronizer and full/empty logic behind a production-style dual-clock FIFO.FPGA Packet Parser
Build a fixed-latency Ethernet/IPv4/UDP parser with field extraction and line-rate statistics without full-frame buffering.Low-Latency Market Data Parser
Build a fixed-format line-rate parser that normalizes market-data messages while tracking deterministic cycle latency.
Open the interactive FPGA Engineer roadmapBuild a configurable SPI master from clock generation and edge timing through MOSI/MISO shifting, chip-select control and complete multi-mode transfers.UART Controller
Build a complete serial controller from timing generation through transmit, receive and loopback integration.Hardware DSP Pipeline
Build a streaming FIR-style datapath with signed MAC arithmetic, sample history, control alignment and saturation.Asynchronous FIFO / CDC
Build the Gray-pointer, synchronizer and full/empty logic behind a production-style dual-clock FIFO.FPGA Packet Parser
Build a fixed-latency Ethernet/IPv4/UDP parser with field extraction and line-rate statistics without full-frame buffering.Low-Latency Market Data Parser
Build a fixed-format line-rate parser that normalizes market-data messages while tracking deterministic cycle latency.