Design Verification
Practice SystemVerilog, assertions, reusable testbench structure and UVM-style checking for verification interviews.
Practice problems
Use these exercises to build the core implementation and verification skills for this path.
always_comb vs always_ff
Identify the correct procedural blocks for combinational and sequential logic.SystemVerilog Interface
Create an interface for a simple ready/valid transaction channel.Valid Must Eventually Handshake
Write an assertion for a ready/valid interface.Reset Clears State
Verify that a synchronous reset clears a counter on the next clock edge.Build a UVM Driver
Implement the core run phase of a UVM driver for a simple transaction.Reference Model Scoreboard
Create a scoreboard that compares observed DUT output against a reference model.Ready/Valid Skid Buffer
Build a one-entry skid buffer that preserves data when downstream backpressure arrives.Backpressure-Safe Ready/Valid Source
Implement a source register that obeys ready/valid protocol semantics.APB Register Peripheral
Build a minimal APB peripheral exposing one 32-bit read/write register.AXI-Lite Write Register Slave
Implement the write side of a single-register AXI-Lite slave.
Identify the correct procedural blocks for combinational and sequential logic.SystemVerilog Interface
Create an interface for a simple ready/valid transaction channel.Valid Must Eventually Handshake
Write an assertion for a ready/valid interface.Reset Clears State
Verify that a synchronous reset clears a counter on the next clock edge.Build a UVM Driver
Implement the core run phase of a UVM driver for a simple transaction.Reference Model Scoreboard
Create a scoreboard that compares observed DUT output against a reference model.Ready/Valid Skid Buffer
Build a one-entry skid buffer that preserves data when downstream backpressure arrives.Backpressure-Safe Ready/Valid Source
Implement a source register that obeys ready/valid protocol semantics.APB Register Peripheral
Build a minimal APB peripheral exposing one 32-bit read/write register.AXI-Lite Write Register Slave
Implement the write side of a single-register AXI-Lite slave.
Projects for this path
Use the projects to combine individual skills into larger portfolio-ready systems.
UVM AXI4-Lite Verification Environment
Build a reusable verification environment with transaction-level stimulus, passive monitoring, scoreboarding, coverage and protocol assertions.AXI Interconnect Verification Environment
Verify the AXI crossbar with randomized multi-master traffic, routing scoreboards, contention tests, protocol assertions and cross coverage.Formal Verification of a Cache Controller
Prove cache invariants around hits, dirty eviction, refill ordering and bounded progress, then add reachability cover goals.Formal Verification of RTL Interfaces
Move beyond simulation by proving FIFO, arbiter and ready/valid properties with assumptions, assertions, bounded progress and reachability goals.APB Peripheral Verification Suite
A compact way to show verification fundamentals before moving to AXI or processor-level work.RISC-V Core Verification
Verify architectural retirement with constrained-random instructions, a reference model, scoreboarding, assertions and functional coverage.
Open the interactive Design Verification roadmapBuild a reusable verification environment with transaction-level stimulus, passive monitoring, scoreboarding, coverage and protocol assertions.AXI Interconnect Verification Environment
Verify the AXI crossbar with randomized multi-master traffic, routing scoreboards, contention tests, protocol assertions and cross coverage.Formal Verification of a Cache Controller
Prove cache invariants around hits, dirty eviction, refill ordering and bounded progress, then add reachability cover goals.Formal Verification of RTL Interfaces
Move beyond simulation by proving FIFO, arbiter and ready/valid properties with assumptions, assertions, bounded progress and reachability goals.APB Peripheral Verification Suite
A compact way to show verification fundamentals before moving to AXI or processor-level work.RISC-V Core Verification
Verify architectural retirement with constrained-random instructions, a reference model, scoreboarding, assertions and functional coverage.