Arm Hardware & CPU Design Interview Practice
Digital logic, CPU microarchitecture, pipeline hazards, cache/TLB reasoning, assertions and AMBA-style interfaces.
Independent preparation resource: HDLForge is not affiliated with Arm. These are practice problems selected for relevant hardware skills; they are not presented as leaked or guaranteed interview questions.
What to practise
Clean digital design, pipelines, AMBA-style interfaces, register structures and CDC-safe control.
Practice set
Work through these problems without looking at solutions first. Explain assumptions, edge cases and verification strategy as if an interviewer were reviewing the design.
Small Register File
Implement a 4-entry register file with one synchronous write port and two asynchronous read ports.One-Hot Traffic-Light FSM
Implement a three-state one-hot finite-state machine.Elastic Pipeline Register
Implement a single-stage pipeline register with an aligned valid bit.Binary to Gray Counter
Build a parameterized binary counter and expose its Gray-code representation.Synchronous FIFO
Implement a synchronous parameterized FIFO with ready/valid-style enqueue and dequeue controls.Backpressure-Safe Ready/Valid Source
Implement a source register that obeys ready/valid protocol semantics.APB Register Peripheral
Build a minimal APB peripheral exposing one 32-bit read/write register.AXI-Lite Write Register Slave
Implement the write side of a single-register AXI-Lite slave.Asynchronous-Assert Reset Synchronizer
Create a two-flop reset synchronizer with asynchronous assertion and synchronous deassertion.Ready/Valid Skid Buffer
Build a one-entry skid buffer that preserves data when downstream backpressure arrives.
Implement a 4-entry register file with one synchronous write port and two asynchronous read ports.One-Hot Traffic-Light FSM
Implement a three-state one-hot finite-state machine.Elastic Pipeline Register
Implement a single-stage pipeline register with an aligned valid bit.Binary to Gray Counter
Build a parameterized binary counter and expose its Gray-code representation.Synchronous FIFO
Implement a synchronous parameterized FIFO with ready/valid-style enqueue and dequeue controls.Backpressure-Safe Ready/Valid Source
Implement a source register that obeys ready/valid protocol semantics.APB Register Peripheral
Build a minimal APB peripheral exposing one 32-bit read/write register.AXI-Lite Write Register Slave
Implement the write side of a single-register AXI-Lite slave.Asynchronous-Assert Reset Synchronizer
Create a two-flop reset synchronizer with asynchronous assertion and synchronous deassertion.Ready/Valid Skid Buffer
Build a one-entry skid buffer that preserves data when downstream backpressure arrives.
Recommended projects
Projects give you deeper material to discuss after the shorter interview exercises.
Three-Stage Pipelined RISC-V Core
Strong evidence of RTL design, control-path reasoning and processor fundamentals.Small RISC-V SoC
Shows that you can move from isolated RTL blocks to a complete programmable system.Parameterized Cache or Memory Controller
Shows stateful RTL beyond simple interview blocks and connects architecture to implementation.
Strong evidence of RTL design, control-path reasoning and processor fundamentals.Small RISC-V SoC
Shows that you can move from isolated RTL blocks to a complete programmable system.Parameterized Cache or Memory Controller
Shows stateful RTL beyond simple interview blocks and connects architecture to implementation.
How to use this track
- Start with the RTL and architecture problems to identify weak fundamentals.
- Repeat the set under time pressure and explain your reasoning aloud.
- For every RTL answer, state reset behavior, edge cases and how you would verify it.
- Build one related project deeply enough to discuss architecture, bugs, verification and trade-offs.