NoC / Interconnect Engineer
Build the arbitration, flow-control, buffering and protocol-conversion foundations used in scalable SoC fabrics and networks-on-chip.
Practice problems
Use these exercises to build the core implementation and verification skills for this path.
4-Request Priority Arbiter
A priority arbiter chooses one winner when multiple devices request access to a shared resource at the same time.Ready/Valid Skid Buffer
Build a one-entry skid buffer that preserves data when downstream backpressure arrives.Synchronous FIFO
Implement a synchronous parameterized FIFO with ready/valid-style enqueue and dequeue controls.Backpressure-Safe Ready/Valid Source
Implement a source register that obeys ready/valid protocol semantics.APB Register Peripheral
Build a minimal APB peripheral exposing one 32-bit read/write register.AXI-Lite Write Register Slave
Implement the write side of a single-register AXI-Lite slave.Synchronize Gray Pointers
Move a Gray-coded pointer safely into the opposite clock domain.Async FIFO Full Detection
Detect the wraparound relationship that means the write pointer is one complete buffer ahead of the read pointer.
A priority arbiter chooses one winner when multiple devices request access to a shared resource at the same time.Ready/Valid Skid Buffer
Build a one-entry skid buffer that preserves data when downstream backpressure arrives.Synchronous FIFO
Implement a synchronous parameterized FIFO with ready/valid-style enqueue and dequeue controls.Backpressure-Safe Ready/Valid Source
Implement a source register that obeys ready/valid protocol semantics.APB Register Peripheral
Build a minimal APB peripheral exposing one 32-bit read/write register.AXI-Lite Write Register Slave
Implement the write side of a single-register AXI-Lite slave.Synchronize Gray Pointers
Move a Gray-coded pointer safely into the opposite clock domain.Async FIFO Full Detection
Detect the wraparound relationship that means the write pointer is one complete buffer ahead of the read pointer.
Projects for this path
Use the projects to combine individual skills into larger portfolio-ready systems.
AXI4 Interconnect / Crossbar
Build a two-master, three-slave interconnect with address decoding, fair arbitration, ownership locking, response routing and DECERR handling.AXI Interconnect Verification Environment
Verify the AXI crossbar with randomized multi-master traffic, routing scoreboards, contention tests, protocol assertions and cross coverage.AXI4-Lite Slave Peripheral
Build a realistic memory-mapped RTL peripheral with independent AXI-Lite channels and correct response handling.AXI-Lite to APB Bridge
A realistic SoC integration block that exercises protocol and control-path reasoning.DMA Engine
Build the data-movement engine accelerators need: programmable registers, source/destination sequencing, backpressure, transfer counting and completion interrupts.Asynchronous FIFO / CDC
Build the Gray-pointer, synchronizer and full/empty logic behind a production-style dual-clock FIFO.Small RISC-V SoC
Integrate processor-facing ROM, RAM, GPIO, timer, interrupts and memory-mapped response routing into a compact programmable SoC.
Open the interactive NoC / Interconnect Engineer roadmapBuild a two-master, three-slave interconnect with address decoding, fair arbitration, ownership locking, response routing and DECERR handling.AXI Interconnect Verification Environment
Verify the AXI crossbar with randomized multi-master traffic, routing scoreboards, contention tests, protocol assertions and cross coverage.AXI4-Lite Slave Peripheral
Build a realistic memory-mapped RTL peripheral with independent AXI-Lite channels and correct response handling.AXI-Lite to APB Bridge
A realistic SoC integration block that exercises protocol and control-path reasoning.DMA Engine
Build the data-movement engine accelerators need: programmable registers, source/destination sequencing, backpressure, transfer counting and completion interrupts.Asynchronous FIFO / CDC
Build the Gray-pointer, synchronizer and full/empty logic behind a production-style dual-clock FIFO.Small RISC-V SoC
Integrate processor-facing ROM, RAM, GPIO, timer, interrupts and memory-mapped response routing into a compact programmable SoC.