Hardware Design Practice Problems
Use this path when you want broad hardware-design practice rather than a single topic. It starts with synthesizable RTL, then adds interfaces, verification, FPGA concerns and architecture reasoning.
How to use this practice path
Stage 1
Start with combinational and sequential RTL fundamentals.
Start with combinational and sequential RTL fundamentals.
Stage 2
Move into FIFOs, register files, arbiters and protocol state machines.
Move into FIFOs, register files, arbiters and protocol state machines.
Stage 3
Add SystemVerilog, assertions and UVM-style checking.
Add SystemVerilog, assertions and UVM-style checking.
Stage 4
Finish with CDC, FPGA implementation concerns and architecture problems.
Finish with CDC, FPGA implementation concerns and architecture problems.
Problems to solve
2:1 Multiplexer
Design a synthesizable 2:1 multiplexer.
Parameterized Counter
Build a parameterized synchronous up-counter with reset.
Shift Register
Build a parameterized register that stores multiple bits and can shift its contents by one position on each clock edge.
Rising Edge Detector
Generate a one-cycle pulse whenever an input signal transitions from 0 to 1.
always_comb vs always_ff
Identify the correct procedural blocks for combinational and sequential logic.
Reset Clears State
Verify that a synchronous reset clears a counter on the next clock edge.
Button Debouncer
Create a synchronous button debouncer suitable for an FPGA.
Traffic Light FSM
Design a finite-state machine controlling a simple traffic light sequence.
Parameterized PWM Generator
Generate a PWM waveform from an unsigned duty-cycle input.
Clock-Enable Data Register
Model the FPGA-friendly alternative to fabric clock gating: a register controlled by clock enable.
3-to-8 Decoder
Decode a 3-bit input into a one-hot 8-bit output.
16-bit Magnitude Comparator
Compare two unsigned 16-bit values.
Even-Parity Generator
Generate the parity bit required to make an 8-bit word have even parity.
Register with Clock Enable
Build an 8-bit register that updates only when enable is high.
Toggle Flip-Flop
Toggle an output bit whenever toggle_en is asserted.
Sticky Status Flag
Latch an event until software explicitly clears it.
Start/Busy/Done Controller
Implement a standard operation-control shell with start, busy and one-cycle done.
Clock and Reset Generator
Create reusable testbench clock and reset stimulus.
Reusable Stimulus Task
Encapsulate repeated stimulus in a SystemVerilog task.
Self-Checking Adder Testbench
Make a simple combinational testbench report mismatches automatically.
Simulation Timeout Watchdog
Prevent a hung test from running forever.
Monitor-Only Interface Modport
Expose a read-only monitor view of an interface.
One-Hot Grant Assertion
Assert that an arbiter never grants more than one requester.
No FIFO Overflow Assertion
Assert that a write is never attempted while the FIFO is full.
Interview routine
For each problem, first restate the requirement and assumptions. Then write the RTL, assertion, verification component or architecture derivation without looking at a solution. Before running anything, list at least three edge cases. Finish by explaining how you would verify the result and what trade-offs you made.
Keep going
Use the interactive HDLForge problem workspace, browse company-style tracks, or choose a hardware project that uses the same skills.